Increases in IC speed have resulted in a new class of ICs with HSS inputs and outputs. These HSS inputs and outputs currently operate at speeds of 622 Mbits/sec to 2-6 Gbits/sec, and next generation HSS inputs and outputs may reach speeds of 10-13 Gbits/sec. There are at least two different types of interfaces requiring HSS inputs and outputs. One type of interface is for communications, where a HSS differential input/output pair is referred to as a “lane,” and wherein a clock might be embedded in the signal. The second type of interface requiring HSS inputs and outputs is found in memory devices communicating with a processor through a HSS memory interface. These memory interfaces may include a forwarded clock that is sent separate from, but along with, the data being transmitted.
As shown in the simplified exemplary stressed eye pattern 100 of FIG. 1, as the amount of jitter present in a HSS signal increases, a HSS data transition 102 may change (i.e. move left or right in time) and the eye 104 may begin to close. In addition, the eye 104 may also begin to close depending on the high or low voltage levels 106 and 108, respectively, of the HSS signal. Note that the eye 104 might have a width of as little as 150-500 picoseconds, so it doesn't take much jitter or other limitations to the bandwidth of the transmission medium to cause a device to have difficulty receiving the HSS signal. Circuitry is therefore often built into the transmit and receive circuitry of HSS interfaces to improve data transmission and reception. Pre-emphasis circuitry is normally used in the transmit circuit to boost signal levels, and equalization is used in the receive circuit to open up the eye and ensure that data can be received.
It is desirable to test the characteristics of the HSS interfaces on Automatic Test Equipment (ATE). Such tests are designed to determine whether these HSS interfaces are working properly—not necessarily to verify the data that is passing through, but rather that the interface circuitry in each HSS interface can detect and process data transitions even at the limits of jitter and voltage level requirements.
For example, as illustrated in FIG. 2a, by injecting data-dependent jitter or changing the high or low voltage levels (see reference character 200) of a HSS signal 202 generated within the ATE 204 and destined for a HSS input 206 of a DUT 208, the eye of the input signal can be closed up to a certain extent, and it can be determined whether the receiver in the HSS input is capable of receiving the data being sent even with the degraded input signal. Although in one embodiment of the present invention, detection logic 238 in the DUT 208 is able to detect if the signal was received properly, in another embodiment the DUT then sends the received HSS signal 202 back to the ATE 204 on line 226. In the latter case, the ATE 204 then detects the serial bit stream and compares it to the generated bit stream at device speeds using detection logic 228 to determine if the signals were received and properly transmitted back to the ATE by the DUT 208.
One way to generate HSS test signals is by using a Linear Feedback Shift Register (LFSR) 222 to generate a Pseudo Random Bit Stream (PRBS) 224 which is then sent to the DUT 208. Note that the LFSR 222 of FIG. 2a is merely symbolic, and does not represent an actual digital circuit. Actual LFSRs, not shown in FIG. 2a, are well-understood by those skilled in the art. The DUT 208 then generates a HSS output 226 based on the received PRBS 224. LFSRs 222 are advantageous because they provide a simple means to generate a serial bit stream, and provide enough data transitions to enable the ATE 204 to recover the embedded clock (if any) from the data stream and test for data-dependent jitter. Another type of signal that can test data-dependent jitter is the IEEE 802.3ae compliant Continuous Jitter test pattern (CJpat), which is designed to exercise clock recovery circuits and get as much data-dependent jitter out of a short waveform as possible. Signals read from memory can also be used to test data-dependent jitter.
As illustrated in the example of FIG. 2b, conventional ATE systems 210 may also test HSS signals by providing a path that allows a HSS output 212 from the DUT 214 (generated using a LFSR or other logic 230) to be selectively switched or looped back to a single HSS input 216 of the DUT. This is often called loopback. These loopback tests are designed to simulate various levels of jitter and voltage levels, so that when the DUT 214 generates a signal 218 that is received into the ATE 210, the signal is sent back out to the DUT with some added jitter or changed voltage levels (see reference character 220) to stress the receiver of the HSS input 216 and determine whether it is working properly. The DUT 214 receives the loopback signal and performs comparisons (see reference character 232) to determine if the signals were transmitted and received properly by the DUT. Note that testing at device speeds limits the type of circuits that can be used to implement the loopback circuitry. The transmitter of a HSS output 212 can also be tested in a limited manner in the ATE 210 by measuring the voltage levels coming out of the transmitter, and measuring current and output jitter at Direct Current (DC) voltage levels.
It is desirable in the loopback configuration of FIG. 2b to have the capability to loop back any HSS output from the DUT 214 to any HSS input of the DUT. Conventional mechanisms for doing this utilize analog or high speed digital switches 234. However, analog switching presents loading problems as the signals are passed through multiple relays, and output driving problems if a single signal is to be routed to multiple DUT inputs. High speed digital solutions require complex, special purpose, high speed circuitry. In either case, a switching network to switch these signals directly requires a large bandwidth and is very costly. In addition, such loopback configurations are only capable of looping back a single DUT HSS output to a single DUT HSS input.
Note that one alternative to the loopback circuitry of FIG. 2b is a single wire. However, single wire loopback circuits do not allow for the test signal to be applied to a selectable HSS input or multiple HSS inputs, do not allow for jitter or signal levels to be adjusted (i.e. they are limited by any adjustments that can be made by the transmitter of the DUT), and also require more Built-In Self Test (BIST) capabilities in the DUT.
Therefore, there is a need for loopback circuitry that is capable of connecting a DUT HSS output to multiple DUT HSS inputs, and doing so at lower speeds to enable its implementation in a wider variety of lower cost devices with reduced pin counts.